Conventional non-volatile memory (NVM) cells are routinely used in electronic circuitry, such as electronic consumer devices. However, fabricating conventional NVM cells using low-cost Complimentary Metal Oxide Semiconductor (CMOS) techniques presents various problems. For example, CMOS-compatible NVM cells are being scaled to smaller and smaller sizes, and the smaller sizes often create retention problems in memory cells. This means that the memory cells are often unable to retain their programming for a desired amount of time (such as ten years or more), so data stored in the memory cells can be prematurely lost. A common approach to circumvent this problem is to deposit an extra layer of gate oxide during fabrication of the memory cells. Unfortunately, this increases the complexity of the fabrication process and the cost of the memory cells. Moreover, multi-layer gate oxides often increase leakage currents in the memory cells, which can interfere with the operation of the memory cells.